Question: – 2. (a) What is the Structure of an 8086/8088 Assembly Language program ? Outline the purpose of each element.

Answer: -Structure of an 8086/8088 Assembly Language program

Assembly level programming is very important to low-level embedded system design is used to access the processor instructions to manipulate hardware. It is a most primitive machine level language is used to make efficient code that consumes less number of clock cycles and takes less memory as compared to the high-level programming language. It is a complete hardware oriented programing language to write a program the programmer must be aware of embedded hardware. Here, we are providing basics of assembly level programming 8086.

Assembly Level Programming 8086

The assembly programming language is a low-level language which is developed by using mnemonics. The microcontroller or microprocessor can understand only the binary language like 0’s or 1’s therefore the assembler convert the assembly language to binary language and store it the memory to perform the tasks. Before writing the program the embedded designers must have sufficient knowledge on particular hardware of the controller or processor, so first we required to know hardware of 8086 processor.

8086 Processor Architecture

The 8086 is a processor that is represented for all peripheral devices such as serial bus , and RAM and ROM, I/O devices and so on which are all externally connected to CPU by using a system bus. The 8086 microprocessor has CISC based architecture, and it has peripherals like 32 I/O, Serial communication, memories and counters/timers. The microprocessor requires a program to perform the operations that require a memory for read and save the functions.

The assembly level programming 8086 is based on the memory registers. A Register is the main part of the microprocessors and controllers which are located in the memory that provides a faster way of collecting and storing the data. If we want to manipulate data to a processor or controller by performing multiplication, addition, etc., we cannot do that directly in the memory where need registers to process and to store the data. The 8086 microprocessor contains various kinds of registers that can be classified according to their instructions such as;

General purpose registers: The 8086 CPU has consisted 8-general purpose registers and each register has its own name as shown in the figure such as AX, BX, CX, DX, SI,DI, BP, SP . These all are 16-bit registers where four registers are divided into two parts such as AX, BX, CX, and DX which is mainly used to keep the numbers.
Special purpose registers: The 8086 CPU has consisted 2- special function registers such as IP and flag registers. The IP register point to the current executing instruction and always works to gather with the CS segment register. The main function of flag registers is to modify the CPU operations after mechanical functions are completed and we cannot access directly
Segment registers: The 8086 CPU has consisted 4- segment registers such as CS, DS, ES, SS which is mainly used for possible to store any data in the segment registers and we can access a block of memory using segment registers

Simple Assembly Language Programs 8086

The assembly language programming 8086 has some rules such as

The assembly level programming 8086code must be written in upper case letters
The labels must be followed by a colon, for example: label:
All labels and symbols must begin with a letter
All comments are typed in lower case
The last line of the program must be ended with the END directive

8086 processors have two other instructions to access the data, such as WORD PTR – for word (two bytes), BYTE PTR – for byte.

Op-code: A single instruction is called as an op-code that can be executed by the CPU. Here the ‘MOV’ instruction is called as an op-code.

Operands: A single piece data are called operands that can be operated by the op-code. Example, subtraction operation is performed by the operands that are subtracted by the operand.
Syntax: SUB b, c

8086 microprocessor assembly language programs

1. Write a Program For Read a Character From The Keyboard

MOV ah, 1h //keyboard input subprogram

INT 21h // character input
// character is stored in al
MOV c, al //copy character from alto c

2. Write a Program For Reading and Displaying a Character

MOV ah, 1h           // keyboard input subprogram
INT 21h           //read character into al
MOV dl, al           //copy character to dl
MOV ah, 2h           //character output subprogram
INT 21h           // display character in dl

3. Write a Program Using General Purpose Registers

ORG 100h
MOV AL, VAR1        // check value of VAR1 by moving it to the AL.
LEA BX, VAR1        //get address of VAR1 in BX.
MOV BYTE PTR [BX], 44h // modify the contents of VAR1.
MOV AL, VAR1        //check value of VAR1 by moving it to the AL.
RET
VAR1 DB 22h
END

4. Write a Program For Displaying The String Using Library Functions

include emu8086.inc   //Macro declaration
ORG 100h
PRINT ‘Hello World!’
GOTOXY 10, 5
PUTC 65            // 65 – is an ASCII code for ‘A’
PUTC ‘B’
RET                //return to the operating system.
END                //directive to stop the compiler.

Basic elements of 8086 assembly programming language

8086 assembly programming language instructions

Like we know instruction are the lines of a program that means an action for the computer to execute.
In 8086, a normal instruction is made by an operation code and sometimes operands.
Structure:
OperationCode [Operand1 [, Operand2]]

Operations

the operation are usually logic or arithmetic, but we can also find some special operation like the Jump (JMP) operation.

Principal Arithmetic operationsPrincipal Logic 8086 operations

JUMP operation is an operation that stop the linear execution of the code and indicate the next instruction to execute. It is more complex because it can be unconditional or conditional on the result of some previous operations or on flag value.

Operands

Operands are the parameters of the operation in the instruction. They can be use in 3 way:

Immediate

This means a direct access of a variable that have been declared in the program.

Here we use the content of a register to be a parameter.

Memory

Here we access to the content of a specific part of the memory using a pointer.

Special instructions

Now we will see how to declare a variable and some interrupt instruction.

DECLARATION

In 8086, we need to declare the name of the variable, the size of the variable and it value.
Structure:

VariableName SizeDirective value [ dup (num)]

VariableName : name of your variable.
SizeDirective: word system to define the size, DB will define byte and DW will define a Word(2 byte).
value is your variable value
dub: a system word that means duplicate, used for vector.
num: number of time you duplicate, the size of your vector.

INTERRUPT

Interrupt calls a sub routine of the system to be executed. we will see 2 simple interrupt:

1 – read character from standard input, result is stored in AL.

MOV AH,01hINT 21h

2 – write character to standard output, DL = character to write.

MOV AH,02hINT 21h

8086 assembly programming language directives

from Wikipedia, we can read that “Assembly directives, also called … pseudo-operations …, are instructions that are executed by an assembler at assembly time, not by a CPU at run time. The names of pseudo-operations often start with a dot to distinguish them from machine instructions”
Examples: .MODEL , .STACK , .CODE

8086 assembly program template

Let’s look at an example to understand the structure of a program:

; This is a comment ; 8086 Template example: Hello World ; contant declaration section ; directives for the compiler .MODEL small .STACK .DATA ; variable declaration section message db “Hello World $” ; code section .CODE .STARTUP ; interrup to print a string with $ at the end mov ah,09h mov dx,offset message int 21h .EXIT END ; end of the program

Question: – 2. (b) What is Instruction Cycle? What are various sub-cycles in an Instruction Cycle? Also outline the steps performed during each of these sub-cycles.

Answer: -Instruction Cycle

An instruction cycle, also known as fetch-decode-execute cycle is the basic operational process of a computer. This process is repeated continuously by CPU from boot up to shut down of computer

An instruction cycle (sometimes called fetch-decode-execute cycle) is the basic operation cycle of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction requires, and carries out those actions.
This cycle is repeated continuously by the central processing unit (CPU), from boot up to when the computer is shut down.
In simpler CPUs, the instruction cycle is executed sequentially: each instruction is completely processed before the next one is started.
In most modern CPUs, the instruction cycle is instead executed concurrently in parallel, as an instruction pipeline: the next instruction starts being processed before the previous instruction is finished, which is possible because the cycle is broken up into separate steps.

Following are the steps that occur during an instruction cycle:

Fetch the Instruction

The instruction is fetched from memory address that is stored in PC(Program Counter) and stored in the instruction register IR. At the end of the fetch operation, PC is incremented by 1 and it then points to the next instruction to be executed

A standard process describes the steps needed for processing to take place. It is called the Fetch – Decode – Execute cycle or sometimes simply called the Fetch-Execute Cycle.
First of all, both the data and the program that acts upon that data are loaded into main memory (RAM) by the operating system. The CPU is now ready to do some work.
The first step the CPU carries out is to fetch some data and instructions (program) from main memory then store them in its own internal temporary memory areas. These memory areas are called ‘registers’.
This is called the ‘fetch’ part of the cycle.
For this to happen, the CPU makes use of a vital hardware path called the ‘address bus’.
The CPU places the address of the next item to be fetched on to the address bus.
Data from this address then moves from main memory into the CPU by travelling along another hardware path called the ‘data bus’.
You could imagine that it is a bit like a boat attendant at a lake calling in customers when their time is up — “Boat number 3, time to come in!”
The ‘address’ of the boat is 3 and the ‘data’ is its content. The boat is parked at a pier, which is like the internal register of the CPU.

Decode the Instruction

The instruction in the IR is executed by the decoder.

The next step is for the CPU to make sense of the instruction it has just fetched. This process is called ‘decode’. The CPU is designed to understand a specific set of commands. These are called the ‘instruction set’ of the CPU. Each make of CPU has a different instruction set. The CPU decodes the instruction and prepares various areas within the chip in readiness of the next step.

Read the Effective Address

If the instruction has an indirect address, the effective address is read from the memory. Otherwise operands are directly read in case of immediate operand instruction.

Step 3 is deciding which operation it is. If this is a Memory operation – in this step the computer checks if it’s a direct or indirect memory operation:
Direct memory instruction – Nothing is being done.
Indirect memory instruction – The effective address is being read from the memory. If this is a I/O or Register instruction – the computer checks its kind and executes the instruction.

Execute the Instruction

The Control Unit passes the information in the form of control signals to the functional unit of CPU. The result generated is stored in main memory or sent to an output device.

The cycle is then repeated by fetching the next instruction. Thus in this way the instruction cycle is repeated continuously.

This is the part of the cycle when data processing actually takes place. The instruction is carried out upon the data (executed). The result of this processing is stored in yet another register. Once the execute stage is complete, the CPU sets itself up to begin another cycle once more.

Question: – 3 (a) What are addressing modes ? What are various types of addressing modes for 8086/8088 microprocessor?

Answer: – Addressing Modes

Addressing Modes– The term addressing modes refers to the way in which the operand of an instruction is specified. The addressing mode specifies a rule for interpreting or modifying the address field of the instruction before the operand is actually executed.

Addressing modes for 8086 instructions are divided into two categories:

1) Addressing modes for data

2) Addressing modes for branch

The 8086 memory addressing modes provide flexible access to memory, allowing you to easily access variables, arrays, records, pointers, and other complex data types. The key to good assembly language programming is the proper use of memory addressing modes.

An assembly language program instruction consists of two parts

The memory address of an operand consists of two components:

IMPORTANT TERMS

Starting addressof memory segment.
Effective address or Offset: An offset is determined by adding any combination of three address elements: displacement, base and index.
- Displacement: It is an 8 bit or 16 bit immediate value given in the instruction.
- Base: Contents of base register, BX or BP.
- Index: Content of index register SI or DI.

According to different ways of specifying an operand by 8086 microprocessor, different addressing modes are used by 8086.

Addressing modes used by 8086 microprocessor are discussed below:

Immediate mode: In immediate addressing the operand is specified in the instruction itself. In this mode the data is 8 bits or 16 bits long and data is the part of instruction.

Example: MOV AL, 35H (move the data 35H into AL register)

Register mode: In register addressing the operand is placed in one of 8 bit or 16 bit general purpose registers. The data is in the register that is specified by the instruction.

Example: MOV AX,CX (move the contents of CX register to AX register)

Register Indirect mode: In this addressing the operand’s offset is placed in any one of the registers BX,BP,SI,DI as specified in the instruction. The effective address of the data is in the base register or an index register that is specified by the instruction.
The 8086 CPUs let you access memory indirectly through a register using the register indirect addressing modes.
MOV AX, [BX](move the contents of memory location s

addressed by the register BX to the register AX)

Auto-increment mode: Effective address of the operand is the contents of a register specified in the instruction. After accessing the operand, the contents of this register are automatically incremented to point to the next consecutive memory location.(R1)+.Example:

Add R1, (R2)+ // ORR1 = R1 +M[R2]R2 = R2 + d

Useful for stepping through arrays in a loop. R2 – start of array d – size of an element

Auto-decrement mode: Effective address of the operand is the contents of a register specified in the instruction. Before accessing the operand, the contents of this register are automatically decremented to point to the previous consecutive memory location. –(R1)Example:

Add R1,-(R2) //ORR2 = R2-dR1 = R1 + M[R2]

Auto decrement mode is same as auto increment mode. Both can also be used to implement a stack as push and pop . Auto increment and Auto decrement modes are useful for implementing “Last-In-First-Out” data structures.

Direct Mode: The operand’s offset is given in the instruction as an 8 bit or 16 bit displacement element. In this addressing mode the 16 bit effective address of the data is the part of the instruction.

Branch Related addressing modes:

Intrasegment Direct: The effective branch address is sum of 8 or 16 bit displacement and the current contents of IP(Instruction Pointer).It can be used with either conditional or unconditional branching.
Intrasegment Indirect: The effective branch address is contents of register or memory location that is accessed using any of the data related addressing mode except immediate mode. It can be used only for unconditional branch instruction.
Intersegment Direct: Replaces the content of IP with part of the instruction and the contents of CS with another part of the instruction. This mode is provide a way of branching from one code segment to another.
Intersegment Indirect: Replaces the contents of IP and CS with the contents of two consecutive words in memory that are referenced using any one of the data related addressing mode except immediate and register modes.

Various addressing modes of 8086/8088

1) Register Addressing mode

2) Immediate Addressing mode

3) Register Indirect Addressing mode

4) Direct Addressing mode

5) Indexed Addressing mode

6) Base Relative Addressing mode

7) Base Indexed Addressing mode

Register Addressing Mode

1. Register Addressing Mode: In this addressing mode, the source of data or destination of result is Register. In this type of addressing mode the name of the register is given in the instruction where the data to be read or result is to be stored.
Example: ADD A, R5 ( The instruction will do the addition of data in Accumulator with data in register R5)

3. Register Indirect Addressing Mode: In Register Indirect Addressing Mode, as its name suggests the data is read or stored in register indirectly. That is, we provide the register in the instruction, in which the address of the other register is stored or which points to other register where data is stored or to be stored.
Example: MOV A, @R0 ( This instruction will move the data to accumulator from the register whose address is stored in register R0 ).

Data transfer using registers is called register addressing mode. Here operand value is present in register. For example

MOV AL,BL;

MOV AX,BX;

Immediate Addressing mode

4. Immediate Addressing Mode : In Immediate Addressing Mode , the data immediately follows the instruction. This means that data to be used is already given in the instruction itself.
Example: MOV A, #25H ( This instruction will move the data 25H to Accumulator. The # sign shows that preceding term is data, not the address.)

When data is stored in code segment instead of data segment immediate addressing mode is used. Here operand value is present in the instruction. For example

MOV AX, 12345;

Direct Addressing mode

6. Direct Addressing Mode: In this type of Addressing Mode, the address of data to be read is directly given in the instruction. In case, for storing result the address given in instruction is used to store the result.
Example: MOV A, 46H ( This instruction will move the contents of memory location 46H to Accumulator)

When direct memory address is supplied as part of the instruction is called direct addressing mode. Operand offset value with respect to data segment is given in instruction. For example

MOV AX, [1234];

ADD AX, [1234];

Register Indirect Addressing mode

Here operand offset is given in a cpu register. Register used are BX, SI(source index), DI(destination index), or BP(base pointer). BP holds offset w.r.t Stack segment, but SI,DI and BX refer to data segment. For example

MOV [BX],AX;

ADD AX, [SI];

Indexed Addressing mode

8. Index Addressing Mode: Offset is added to the base index register to form the effective address if the memory location.This Addressing Mode is used for reading lookup tables in Program Memory. The Address of the exact location of the table is formed by adding the Accumulator Data to the base pointer.
Example: MOVC, @A+DPTR ( This instruction will move the data from the memory to Accumulator; the address is made by adding the contents of Accumulator and Data Pointer.

Here operand offset is given by a sum of a value held in either SI, or DI register and a constant displacement specified as an operand. For example

Lets take arrays as an example. This is very efficient way of accessing arrays.

My_array DB ‘1’, ‘2’, ‘3’,’4,’5’;

MOV SI, 3;

MOV AL, My_array[3];

So AL holds value 4.

Base Relative Addressing mode

Operand offset given by a sum of a value held either in BP, or BX and a constant offset sepecified as an operand. For example

MOV AX,[BP+1];

JMP [BX+1];

Base Indexed

Here operand offset is given by sum of either BX or BP with either SI or DI. For example

MOV AX, [BX+SI]

JMP [BP+DI]

Question: – 3(b) What is meant by an Instruction Set? What are the element of Instruction? How an Instruction an represented? Explain.

Answer: -Instruction Set

The instruction set, also called instruction set architecture (ISA), is part of a computer that pertains to programming, which is basically machine language. The instruction set provides commands to the processor, to tell it what it needs to do. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and exception handling, and external I/O.

An example of an instruction set is the x86 instruction set, which is common to find on computers today. Different computer processors can use almost the same instruction set while still having very different internal design. Both the Intel Pentium and AMD Athlon processors use nearly the same x86 instruction set. An instruction set can be built into the hardware of the processor, or it can be emulated in software, using an interpreter. The hardware design is more efficient and faster for running programs than the emulated software version. An instruction set is a group of commands for a CPU in machine language. The term can refer to all possible instructions for a CPU or a subset of instructions to enhance its performance in certain situations.

All CPUs have instruction sets that enable commands to the processor directing the CPU to switch the relevant transistors. Some instructions are simple read, write and movecommands that direct data to different hardware.

In CISC (Complex Instruction Set Computer) processors there is also a microcode layer, which involves programmable instructions stored in fast memory that may be updated. The RISC (Reduced Instruction Set Computer) architecture, on the other hand, has hard-wired control; it does not require microcode but has a greater base instruction set.

Enhancement instruction sets are more familiar to users as they have often been used in marketing a given CPU. Examples of this go back to the Pentium 166Mhz with MMXtechnologies marketed for enhancing Intel CPU multimedia performance.

MMX stands for MultiMedia eXtenstions, and refers to the extended instruction set. Other examples include MMX+, 3DNow!, 3DNow!+, SSE, SSE2, SSSE3, SSE4.1, SSE4A, AVX, AVX2 and XOP.

Examples of instruction set

ADD – Add two numbers together.
COMPARE – Compare numbers.
IN – Input information from a device, e.g., keyboard.
JUMP – Jump to designated RAM address.
JUMP IF – Conditional statement that jumps to a designated RAM address.
LOAD – Load information from RAM to the CPU.
OUT – Output information to device, e.g., monitor.
STORE – Store information to RAM.

Instruction Representation

Within the computer, each instruction is represented by a sequence of bits. The instruction is divided into fields, corresponding to the constituent elements of the instruction. The instruction format is highly machine specific and it mainly depends on the machine architecture. A simple example of an instruction format is shown in the Figure 4.8. It is assume that it is a 16-bit CPU. 4 bits are used to provide the operation code. So, we may have to 16 (2⁴ = 16) different set of instructions. With each instruction, there are two operands. To specify each operands, 6 bits are used. It is possible to provide 64 ( 2⁶ = 64 ) different operands for each operand reference.

It is difficult to deal with binary representation of machine instructions. Thus, it has become common practice to use a symbolic representation of machine instructions.

Opcodes are represented by abbreviations, called mnemonics, that indicate the operations.
Common examples include:

ADD         Add
SUB         Subtract
MULT       Multiply
DIV          Division
LOAD      Load data from memory to CPU
STORE    Store data to memory from CPU.

This article is contributed by Tarun Jangra. Please write comments if you find anything incorrect, or you want to share more information about the topic discussed above.

click here for Unit-II

Visitors 277